A Hardware Engine for Genetic AlgorithmsTechnical Report UNL - CSE - 97 - 001 University of Nebraska - LincolnJuly 4 , 1997 Stephen

A genetic algorithm (GA) is an optimization method based on natural selection. Genetic algorithms have been applied to many hard optimization problems including VLSI layout optimization, boolean satis ability, power system control, fault detection, control systems, and signal processing. GAs have been recognized as a robust general-purpose optimization technique. But application of GAs to increasingly complex problems can overwhelm software implementations of GAs, causing unacceptable delays in the optimization process. This is true of any non-trivial application of GAs if the search space is large or if real-time performance is necessary. It follows that a hardware implementation of a GA is desirable for application to problems too complex for software-based GAs. Hardware's speed advantage and its ability to parallelize o er great rewards to genetic algorithms. Speedups of 1{2 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of eld-programmable gate arrays (FPGAs). Since most of the GA's operations are simple, a hardware implementation is feasible. Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). In hardware, reprogrammability is possible with FPGAs. Thus an FPGA-based GA is both feasible and desirable. A fully functional self-contained hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be speci ed by the user. An analysis of the design is given that identi es the bottleneck of the HGA's pipeline under varying conditions. Simulation results of the HGA are also presented. A prototype HGA is described and compared to a similar GA implemented in software. In our tests, the prototype and simulations took two to ve percent as many clock cycles to run as the software-based GA. Suggested design improvements could dramatically increase the HGA's speed even further. Finally, we give other potential applications of the HGA which are feasible with current FPGA technology.